Second Workshop on Pioneering Processor Paradigms

Introduction

Innovations in instruction set architecture (ISA), processor microarchitecture and supportive advances in circuit design, compilers, semiconductor technology, pre-silicon specification, modeling and validation have all been essential elements of the computer systems revolution that has transformed human society so dramatically over the last six decades or more. In the late CMOS era, with power and reliability walls already causing major paradigm shifts, the need for new innovations in cross-layer, hardware-software design and modeling are being called for to help keep the IT industry moving and growing at historical rates.

In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. With this in mind and after the resounding success of the first edition, we present the second edition of the workshop on pioneering processor paradigms (P³). With the help of true pioneers as well as budding new researchers, P³ will take a retrospective look at how past technological hurdles were circumvented through major innovations. The goal is to learn from the past in devising new solution strategies for the future.

The P³ workshop will offer a number of invited talks from true pioneers, reviewed selections from the new generation of researchers and teachers who are eager to take a retrospective look into surveying past pioneering work that can teach us a lesson about solution strategies of the future as well as reviewed selections of research on new processor paradigms.

Final papers will be posted in an online proceedings (on the workshop website).

Important dates

• Submission deadline: December 31st, 2017 January 12nd, 2018
• Notification of acceptance: January 14th, 2018
• Final paper submission: February 11st, 2018
• Workshop date: February 25th, 2018

Program Committee

• Lluc Alvarez, Barcelona Supercomputing Center
• Ramon Bertran, IBM Research
• Pradip Bose, IBM Research
• Jose Cano Reyes, University of Edinburgh
• Robert Montoye, IBM Research
• Carlos Villavieja, Google
• John-David Wellman, IBM Research

Motivation

The design and development of computer processors as an industry has a relatively shorter history than many other industries, but over those ~60 years there have been a number of major disruptive, transformational developments and changes in the technologies, methodologies, architectures, implementations, design processes, and even goals. The processor design community has always been highly focused on the future, on pushing technology and implementations forward into new areas, exploiting new approaches and ideas, and generally progressing forward. We feel, however, that it is important at times to look back at the history, to study what has come before, and to glean new insights to use in the pursuit of the future.

We now find ourselves in the late CMOS silicon era, where the CMOS technology is growing ever closer to fundamental physical limits, and there are clearly visible constraints on (and increasing pressures to) the chip area and power. As designs are pushing ever forward in CMOS, additional pressures appear to limit the effectiveness of time-tested techniques (e.g. reliability issues limit the ability to further reduce voltage and current points in devices, cross-talk limits how physically close devices can be laid out, etc.). Additionally, the performance uplift from each technology generation is less than in the prior generations, with no clear end to this trend in sight. In essence, the challenges of future processor design appear to be growing.

The Workshop on Pioneering Processor Paradigms intends to reflect upon important transition points of our shared historic past, and to learn from these historic inflection points lessons that can improve our insights into the present and future of processor design. As one reflects on the current state of technology and processor design, and in consideration of the history of computer processor research and design, one can find similar points in the past when a shift in paradigm was required in order to go forward.

Innovations in instruction set architecture (ISA), processor microarchitecture and supportive advances in circuit design, compilers, semiconductor technology, pre-silicon specification, modeling and validation have all been essential elements of the computer systems revolution that has transformed human society so dramatically over the last six decades or more. In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. Processor design has faced a number of prior cases where technology "ran into a wall" -- consider the transition from discrete to integrated circuits, and later from bipolar technologies to CMOS. In the late CMOS era, with power and reliability walls already causing major paradigm shifts, the need for new innovations in cross-layer, hardware-software design and modeling are being called for to help keep the IT industry moving and growing at historical rates.

With the help of true pioneers as well as budding new researchers, -- the Workshop on Pioneering Processor Paradigms -- will take a retrospective look at how past technological hurdles were circumvented through major innovations. The goal here is to take lessons from the past and apply them to the present in order to devise new solution strategies for the future of our industry.