Introduction

Innovations in instruction set architecture (ISA), processor microarchitecture and supportive advances in circuit design, compilers, semiconductor technology, pre-silicon specification, modeling and validation have all been essential elements of the computer systems revolution that has transformed human society so dramatically over the last six decades or more. In the late CMOS era, with power and reliability walls already causing major paradigm shifts, the need for new innovations in cross-layer, hardware-software design and modeling are being called for to help keep the IT industry moving and growing at historical rates.

In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. With this in mind and after the resounding success of the first edition, we present the second edition of the workshop on pioneering processor paradigms (P3). With the help of true pioneers as well as budding new researchers, P3 will take a retrospective look at how past technological hurdles were circumvented through major innovations. The goal is to learn from the past in devising new solution strategies for the future.

The P3 workshop will offer a number of invited talks from true pioneers, reviewed selections from the new generation of researchers and teachers who are eager to take a retrospective look into surveying past pioneering work that can teach us a lesson about solution strategies of the future as well as reviewed selections of research on new processor paradigms.

Final papers will be posted in an online proceedings (on the workshop website).

Important dates

  • Submission deadline: December 31st, 2017 January 12nd, 2018
  • Notification of acceptance: January 14th, 2018
  • Final paper submission: February 11st, 2018
  • Workshop date: February 25th, 2018

Program Committee

  • Lluc Alvarez, Barcelona Supercomputing Center
  • Ramon Bertran, IBM Research
  • Pradip Bose, IBM Research
  • Jose Cano Reyes, University of Edinburgh
  • Robert Montoye, IBM Research
  • Carlos Villavieja, Google
  • John-David Wellman, IBM Research

Motivation

The design and development of computer processors as an industry has a relatively shorter history than many other industries, but over those ~60 years there have been a number of major disruptive, transformational developments and changes in the technologies, methodologies, architectures, implementations, design processes, and even goals. The processor design community has always been highly focused on the future, on pushing technology and implementations forward into new areas, exploiting new approaches and ideas, and generally progressing forward. We feel, however, that it is important at times to look back at the history, to study what has come before, and to glean new insights to use in the pursuit of the future.

We now find ourselves in the late CMOS silicon era, where the CMOS technology is growing ever closer to fundamental physical limits, and there are clearly visible constraints on (and increasing pressures to) the chip area and power. As designs are pushing ever forward in CMOS, additional pressures appear to limit the effectiveness of time-tested techniques (e.g. reliability issues limit the ability to further reduce voltage and current points in devices, cross-talk limits how physically close devices can be laid out, etc.). Additionally, the performance uplift from each technology generation is less than in the prior generations, with no clear end to this trend in sight. In essence, the challenges of future processor design appear to be growing.

The Workshop on Pioneering Processor Paradigms intends to reflect upon important transition points of our shared historic past, and to learn from these historic inflection points lessons that can improve our insights into the present and future of processor design. As one reflects on the current state of technology and processor design, and in consideration of the history of computer processor research and design, one can find similar points in the past when a shift in paradigm was required in order to go forward.

Innovations in instruction set architecture (ISA), processor microarchitecture and supportive advances in circuit design, compilers, semiconductor technology, pre-silicon specification, modeling and validation have all been essential elements of the computer systems revolution that has transformed human society so dramatically over the last six decades or more. In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. Processor design has faced a number of prior cases where technology "ran into a wall" -- consider the transition from discrete to integrated circuits, and later from bipolar technologies to CMOS. In the late CMOS era, with power and reliability walls already causing major paradigm shifts, the need for new innovations in cross-layer, hardware-software design and modeling are being called for to help keep the IT industry moving and growing at historical rates.

With the help of true pioneers as well as budding new researchers, -- the Workshop on Pioneering Processor Paradigms -- will take a retrospective look at how past technological hurdles were circumvented through major innovations. The goal here is to take lessons from the past and apply them to the present in order to devise new solution strategies for the future of our industry.

Submission Deadline

December 31st, 2017
January 12nd, 2018

Notification of acceptance
January 14th, 2018

Final paper submission
February 11st, 2018

Workshop date
February 25th, 2018

Call for Contributions

The workshop on pioneering processor paradigms invites survey (or tutorial)-like submissions for review. The ideal paper would highlight a single pioneering paper (or set of papers) constituting a major processing, design, modeling or software paradigm shift in the past. In addition to explaining the context and basic concepts articulated in such work, the author(s) should draw relevant conclusions about how this pioneering work could or should influence computing paradigms of the future. Original research on new/unconventional processor paradigms will also be considered.

Note: Ph.D dissertation research topic proposals from (junior graduate students) that contain a survey of a key paper or two to build up the motivational justification of the proposal are quite welcome, for example.

Topics

Example topic areas include (but are not limited to):

  • Processing and cache taxonomy papers.
  • RISC architectures and CISC-to-RISC dynamic translation support.
  • Processor pipelining, super scalar processing and branch prediction innovations.
  • Register renaming, out-of-order execution and precise interruption.
  • Cycle-accurate processor performance modeling.
  • Innovations in floating point arithmetic units and vector/SIMD acceleration.
  • VLIW architectures.
  • Multi-threading, multiscalar and speculative multi-threading.
  • Homogeneous and heterogeneous multi-core processors; accelerator-enabled efficiency boost.
  • Power, temperature, and reliability-aware computing – with associated modeling innovations.
  • Compiler innovations in support of novel microarchitectural paradigms.
  • Circuit design innovations in support of (micro)-architectural paradigm shifts.

Submit Your Contribution

Papers reporting original research results pertaining to the mentioned and related topics are solicited.

Submission length & format

Full paper manuscripts must be in English of up to 6 pages (using the IEEE two-column format).

Format Template

The online submission site is EasyChair. If web submission is not possible, please contact the program co-chairs for alternate arrangements.

Submit

If you have questions regarding submission, contact us

Contact

Advance Program

Location: Europa 5

Download Program (pdf format)

  • 8:30 AM – 8:40 AM: Welcome and Introduction Pradip Bose; on behalf of the workshop co-organizers: (Ramon Bertran, Pradip Bose, Robert Montoye, John-David Wellman)
  • 8:40 AM – 9:40 AM: Keynote – I: Mikko H. Lipasti, MICRO 2017 Test of Time Award, University of Wisconsin - Madison
    • Talk Title: A Brief History of Speculation
  • 9:40 AM – 10:00 AM: Retrospective Survey I
    • On the Evaluation of Computer Architectures
      Mario Badr and Natalie Enright Jerger, University of Toronto
      Paper Presentation
  • 10:00 AM – 10:30 AM: Coffee/Tea Break
  • 10:30 AM – 11:20 AM: Invited Talk: Lluis Vilanova, Technion
    • Talk Title: 40 years since dusk: will hardware capabilities finally make our systems more capable?
  • 11:20 AM – 12:00 AM: New/Exploratory paradigms
    • A Multi-component Branch Predictor Design for Low Resource Budget Processors
      Moumita Das, Ansuman Banerjee and Bhaskar Sardar,Indian Statistical Institute and Jadavpur University
      Paper Presentation
    • FFT implementation using mono-instruction set computer architecture
      Hiroki Shinba and Minoru Watanabe, Shizuoka University
      Paper Presentation
  • 12:00 Noon – 1:30 PM: Lunch
  • 1:30 PM – 2:20 PM: Keynote-II: R. Iris Bahar, Brown University
    • Talk Title: Ventures into Power-Aware Computer Architecture Design
  • 2:20 PM – 3:00 PM: Restrospective Survey II
    • This Architecture Tastes Like Microarchitecture
      Curtis Dunham and Jonathan Beard, ARM Research
      Paper Presentation
    • Project CrayOn: Back to the future for a more General-Purpose GPU?
      Philip Machanick, Rhodes University
      Paper Presentation
  • 3:00 PM – 3:30 PM: Coffee/Tea Break
  • 3:30 PM – 3:50 PM: Retrospective Survey III
    • 45-year CPU evolution: one law and two equations
      Daniel Etiemble, University Paris Saclay
      Paper Presentation
  • 3:50 PM – 4:50 PM: Panel Session
    • Panel title: Retrospective Vision: A Blessing or a Curse?
      Panelists: Daniel Etiemble, Curtis Dunham, Mario Badr, Philip Machanick
      Moderator: TBD
      Panel Description:This panel will discuss and debate the worth of looking back at pioneering processor paradigms of the past. Are such retrospective views of past innovations useful in future research, or can they discourage new researchers from pursuing ideas in that field - because they conclude it to be a mature (or even dead-ended) field? The panel is composed of a range of innovators - from seasoned, senior researchers/practitioners to younger innovators who are quite new as professionals. .
  • 4:50 PM - Recap/discussion; clossing remarks, action items
    • Discussion driven by workshop organizers.
      • Can/should we try a special issue of IEEE Computer (or ACM Communications) to cover selected articles that cover the theme of this workshop?
      • Should we offer WP3 again in the future? At ISCA or MICRO? How can we improve the quality and the end utility?

Invited pioneers keynotes & young researcher invited talk

Please find below the list of the long talks to be given by pioneers and young researchers.

-

Mikko H. Lipasti
(MICRO 2017 Test of Time Award)

Talk: A Brief History of Speculation

-

R. Iris Bahar

(Brown University)

Talk: Ventures into Power-Aware Computer Architecture Design

-

Lluis Vilanova

(Technion)

Talk: 40 years since dusk: will hardware capabilities finally make our systems more capable?

2017
February 25

Vienna
Austria

Organizers

John-David Wellman is a research staff member at IBM T. J. Watson Research Center. He has over 20 years’ of experience at IBM in pre-silicon performance modeling. At present he is a key member of the future z Systems (mainframe) processor microarchitecture concept definition team. He holds a Ph.D from University of Michigan, Ann Arbor.

Robert Montoye is a research staff member at IBM T. J. Watson Research Center. He made pioneering contributions to the industry-first RS/6000 (POWER-1) processor and system – specifically in terms of its floating point engine. He has over 30 years of experience at IBM. He holds a Ph.D from University of Illinois at Urbana-Champaign.

Ramon Bertran is a research staff member at IBM T. J. Watson Research Center. He has worked in power and performance analysis, reliability, and tools and methodology for the investigation of these various aspects during hardware design. He holds a Ph.D from the Polytechnic University of Catalonia (UPC).

Pradip Bose is the manager of Efficient and Resilient Systems at IBM T. J. Watson Research Center. He has over thirty-three years of experience at IBM, and was a member of the pioneering RISC super scalar project at IBM (a pre-cursor to the first RS/6000 system product). He holds a Ph.D from University of Illinois at Urbana-Champaign.

Registration

W3P will be held in conjunction with the 24th IEEE Symposium on High Performance Computer Architecture (HPCA). Refer to the main venue to continue with the registration process.

Event Location

Austria Trend Eventhotel Pyramide
Parkallee 2
2334 Vösendorf
Vienna, Austria

Check main venue site for more information.