Introduction

Innovations in instruction set architecture (ISA), processor microarchitecture and supportive advances in circuit design, compilers, semiconductor technology, pre-silicon specification, modeling and validation have all been essential elements of the computer systems revolution that has transformed human society so dramatically over the last six decades or more. In the late CMOS era, with power and reliability walls already causing major paradigm shifts, the need for new innovations in cross-layer, hardware-software design and modeling are being called for to help keep the IT industry moving and growing at historical rates.

In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. With this in mind and after the resounding success of the first edition, we present the second edition of the workshop on pioneering processor paradigms (P3). With the help of true pioneers as well as budding new researchers, P3 will take a retrospective look at how past technological hurdles were circumvented through major innovations. The goal is to learn from the past in devising new solution strategies for the future.

The P3 workshop will offer a number of invited talks from true pioneers as well as reviewed selections from the new generation of researchers and teachers who are eager to take a retrospective look into surveying past pioneering work that can teach us a lesson about solution strategies of the future.

Important dates

  • Submission deadline: December 31st, 2017
  • Notification of acceptance: January 14th, 2018
  • Final paper submission: February 11st, 2018
  • Workshop date: February 25th, 2018

Program Committee

  • TBD

Motivation

The design and development of computer processors as an industry has a relatively shorter history than many other industries, but over those ~60 years there have been a number of major disruptive, transformational developments and changes in the technologies, methodologies, architectures, implementations, design processes, and even goals. The processor design community has always been highly focused on the future, on pushing technology and implementations forward into new areas, exploiting new approaches and ideas, and generally progressing forward. We feel, however, that it is important at times to look back at the history, to study what has come before, and to glean new insights to use in the pursuit of the future.

We now find ourselves in the late CMOS silicon era, where the CMOS technology is growing ever closer to fundamental physical limits, and there are clearly visible constraints on (and increasing pressures to) the chip area and power. As designs are pushing ever forward in CMOS, additional pressures appear to limit the effectiveness of time-tested techniques (e.g. reliability issues limit the ability to further reduce voltage and current points in devices, cross-talk limits how physically close devices can be laid out, etc.). Additionally, the performance uplift from each technology generation is less than in the prior generations, with no clear end to this trend in sight. In essence, the challenges of future processor design appear to be growing.

The Workshop on Pioneering Processor Paradigms intends to reflect upon important transition points of our shared historic past, and to learn from these historic inflection points lessons that can improve our insights into the present and future of processor design. As one reflects on the current state of technology and processor design, and in consideration of the history of computer processor research and design, one can find similar points in the past when a shift in paradigm was required in order to go forward.

Innovations in instruction set architecture (ISA), processor microarchitecture and supportive advances in circuit design, compilers, semiconductor technology, pre-silicon specification, modeling and validation have all been essential elements of the computer systems revolution that has transformed human society so dramatically over the last six decades or more. In trying to forge a path of innovation, it is sometimes worth examining the past to look for major paradigm shifts in (micro)-architecture, circuits, modeling and software that helped us keep going in the face of past technology-driven disruption points. Processor design has faced a number of prior cases where technology "ran into a wall" -- consider the transition from discrete to integrated circuits, and later from bipolar technologies to CMOS. In the late CMOS era, with power and reliability walls already causing major paradigm shifts, the need for new innovations in cross-layer, hardware-software design and modeling are being called for to help keep the IT industry moving and growing at historical rates.

With the help of true pioneers as well as budding new researchers, -- the Workshop on Pioneering Processor Paradigms -- will take a retrospective look at how past technological hurdles were circumvented through major innovations. The goal here is to take lessons from the past and apply them to the present in order to devise new solution strategies for the future of our industry.

Submission Deadline

December 31st, 2017

Notification of acceptance
January 14th, 2018

Final paper submission
February 11st, 2018

Workshop date
February 25th, 2018

Call for Contributions

The workshop on pioneering processor paradigms invites survey (or tutorial)-like submissions for review. The ideal paper would highlight a single pioneering paper (or set of papers) constituting a major processing, design, modeling or software paradigm shift in the past. In addition to explaining the context and basic concepts articulated in such work, the author(s) should draw relevant conclusions about how this pioneering work could or should influence computing paradigms of the future.

Note: Ph.D dissertation research topic proposals from (junior graduate students) that contain a survey of a key paper or two to build up the motivational justification of the proposal are quite welcome, for example.

Topics

Example topic areas include (but are not limited to):

  • Processing and cache taxonomy papers.
  • RISC architectures and CISC-to-RISC dynamic translation support.
  • Processor pipelining, super scalar processing and branch prediction innovations.
  • Register renaming, out-of-order execution and precise interruption.
  • Cycle-accurate processor performance modeling.
  • Innovations in floating point arithmetic units and vector/SIMD acceleration.
  • VLIW architectures.
  • Multi-threading, multiscalar and speculative multi-threading.
  • Homogeneous and heterogeneous multi-core processors; accelerator-enabled efficiency boost.
  • Power, temperature, and reliability-aware computing – with associated modeling innovations.
  • Compiler innovations in support of novel microarchitectural paradigms.
  • Circuit design innovations in support of (micro)-architectural paradigm shifts.

Submit Your Contribution

Papers reporting original research results pertaining to the mentioned and related topics are solicited. Full paper manuscripts must be in English of up to 6 pages (using the IEEE two-column format).

Format Template

The online submission site is EasyChair. If web submission is not possible, please contact the program co-chairs for alternate arrangements.

Submit

If you have questions regarding submission, contact us

Contact

Program

TBD

Invited pioneers

Please find below the list of the long talks to be given by pioneers and experienced researchers.

TBD

Technical Talks

Please find below the list of short technical presentations

TBD

2017
February 25

Vienna
Austria

Organizers

John-David Wellman is a research staff member at IBM T. J. Watson Research Center. He has over 20 years’ of experience at IBM in pre-silicon performance modeling. At present he is a key member of the future z Systems (mainframe) processor microarchitecture concept definition team. He holds a Ph.D from University of Michigan, Ann Arbor.

Robert Montoye is a research staff member at IBM T. J. Watson Research Center. He made pioneering contributions to the industry-first RS/6000 (POWER-1) processor and system – specifically in terms of its floating point engine. He has over 30 years of experience at IBM. He holds a Ph.D from University of Illinois at Urbana-Champaign.

Ramon Bertran is a research staff member at IBM T. J. Watson Research Center. He has worked in power and performance analysis, reliability, and tools and methodology for the investigation of these various aspects during hardware design. He holds a Ph.D from the Polytechnic University of Catalonia (UPC).

Pradip Bose is the manager of Efficient and Resilient Systems at IBM T. J. Watson Research Center. He has over thirty-three years of experience at IBM, and was a member of the pioneering RISC super scalar project at IBM (a pre-cursor to the first RS/6000 system product). He holds a Ph.D from University of Illinois at Urbana-Champaign.

Registration

W3P will be held in conjunction with the 24th IEEE Symposium on High Performance Computer Architecture (HPCA). Refer to the main venue to continue with the registration process.

Event Location

Austria Trend Eventhotel Pyramide
Parkallee 2
2334 Vösendorf
Vienna, Austria

Check main venue site for more information.